Integrated circuits are designed in a hierarchical manner with building blocks that are used multiple times and connected to each other to perform certain logical functions. Each block or cell consists of active devices and wires connecting them together to form a circuit. Design of integrated circuits takes place in a computer using geometrical shapes representing the individual masks required to fabricate the integrated circuit. The geometrical shapes comprising the layout of the integrated circuit are embedded between successive layers of dielectrics, the technology stack up, forming a three-dimensional structure
Todays integrated circuits consist of billions of devices and interconnect lines. Devices can be classified as actives and passives. Radio frequency (RF) circuits utilise both active and passive devices and interconnects between them. Passive devices such as integrated inductors are essentially interconnect lines with specific layout designed to produce the same electrical properties as their discrete off-chip counterparts. Therefore, they need to be treated in different manner when extraction and verification of the layout of the design is performed prior to fabrication. Such devices may require different extraction and verification steps to ensure accuracy is achieved in the desired frequency of operation.
Historically, off-chip passive devices were modeled by compact models based on closed form expressions and were good enough to model the device behaviour at Printed Circuit Board (PCB) level. Integration of such devices for RF circuit designs requires a distributed model to accurately model electromagnetic effects in gigahertz range frequencies. Model extraction of such devices takes place in the form of a SPICE equivalent RLCk electric network. The estimation of the parasitic capacitance of passive devices and interconnects plays a crucial role in the modeling of the high frequency performance and behaviour of each individual device and the entire circuit
Parasitic extraction and verification is dominated by pattern matching methods employed by commercially available solvers. The integrated circuit is divided into patterns which are matched to a database of precomputed/pre-solved patterns. Other analytical methods that are not based on pattern matching included discretization-based or discretization-free solvers. The former are limited by the size of the integrated circuit. Memory requirements and solution times can be high and prohibitive to very large integrated circuits. Discretization-free solvers are mainly stochastic and bear the advantage a small memory footprint, rapid solution times and predictability of accuracy.
The floating random walk method for capacitance extraction has been utilised in VeloceRaptor/X, manufactured by Helic, Inc. of San Jose, Calif. The accuracy of the algorithm depends on pre-characterised random walk transition domains. Pre-characterisation of all possible combinations of dielectric layers for all transition domain sizes is prohibitive. Classification of the transition domains in such manner so that only those mostly likely to be needed by the random walk algorithm are initially precomputed and stored to memory, improves the accuracy and convergence time of the method. A multi-tier system and method for multi-dielectric transition domain pre-characterisation is presented.
While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.